1. Field of the Invention
The present invention relates to a pulse generating circuit, and more particularly, to a pulse generating circuit for a dynamic random access memory (DRAM) device. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for eliminating a malfunction in operating a DRAM, thereby improving a reliability in the DRAM.
2. Description of the Related Art
In general, the range of an operational frequency of DRAM devices is about several tens MHZ. Since the range of the operational frequency becomes higher, it is constantly broadened. Accordingly, a timing skew among signals controlling the DRAM must be eliminated in order to properly operate in the wide range.
A pulse generating circuit for a DRAM and operation of the same according to a background art will be described with reference to the accompanying drawings.
FIG. 1 is a pulse generating circuit for a DRAM according to the background art. As shown in FIG. 1, the pulse generating circuit for the DRAM includes a delay unit 10 delaying an input signal CLK and outputting a delay signal Z. An AND gate ND1 receiving the input signal CLK and the delay signal Z and generating an output pulse signal CP. The delay unit 10 having the odd number of inverters IN1, IN2 . . . IN2n-1.
The pulse generating circuit for the DRAM according to the background art outputs a predetermined output pulse signal CP regardless of a frequency of the input signal. The operation process is illustrated in FIGS. 2A to 2C and 3A to 3C.
FIG. 2A is an input signal of a high frequency CLK. As shown in FIG. 2B, the delay unit 10 receiving the input signal CLK outputs the delay signal Z. In FIG. 2C, the AND gate ND1 receiving the input signal CLK and the delay signal z generates an output pulse signal CP having a predetermined pulse width td1. A width of the output pulse signal CP is determined only by the number of inverters IN1, IN2, . . . , IN2n-1 of the delay unit 10.
Similarly, FIG. 3A is an input signal of a low frequency CLK'. FIG. 3B illustrates that the delay unit 10 delaying the signal of the low frequency outputs a delay signal Z' delayed for a period the same as the delay time tdl of the input signal of the high frequency CLK. Therefore, the AND gate ND1 receiving the input signal of the low frequency CLK' and the delay signal Z' outputs an output pulse signal CP' identical to the output pulse signal CP generated from the signal of the high frequency CLK. It is because the output pulse signals CP and CP' are determined solely by the number of the inverters IN1, IN2, . . . , IN2n-1.
Regardless of a frequency of the input signal, a width of the output pulse signal from the pulse generating circuit is determined solely by the number of the inverters IN1, IN2, . . . , IN2n-1 included in the delay unit 10 of the pulse generating circuit. In order to control the DRAM, the output pulse signal is generated by receiving the input signal of the high frequency in the pulse generating circuit. The output pulse signal does not generate a timing skew with the other control signals controlling the DRAM and serves to control the DRAM without a malfunction.
However, as the range of the operational frequency of the DRAM is broadened, the input signal in the pulse generating circuit according to the background art generates the output pulse signal by receiving a low frequency to control the DRAM. Thus, the output pulse signal has a pulse width identical to the output pulse signal generated by receiving a high frequency. Therefore, the output pulse signa generates a timing skew with the other control signals generated by the low frequency signal, thereby breaking down the DRAM.